In recent years the increase in capacity of nonvolatile semiconductor storage devices, of which flash memory is representative, has been remarkable, and there have been announcements of the release of products with capacities of approximately 32 Gbytes. In particular, the commodity value as USB memory and as storage for mobile phones is increasing. That is, nonvolatile semiconductor storage devices exploit the inherent superiority of solid-state memory devices as storage for portable music players, with respect to resistance to vibrations, high reliability, and low power consumption, so that such devices are becoming the mainstream of storage for the above mobile or portable music or video commercial products.
On the other hand, separately from the above-described storage applications, vigorous research is also in progress aiming at the realization of so-called “instant-on computers”, or computers which can be started up instantly for use, and which in standby mode have vanishingly small power consumption. This is an attempt to utilize the provision of DRAM, currently used as the main memory of information equipment, with nonvolatile properties; for such applications it is said that the technical specifications demanded of DRAM, that is, (1) switching times of less than 50 ns, and (2) overwrite operations exceeding 1016 cycles, must be satisfied, and in addition the memory must have nonvolatile properties.
As candidates for such next-generation nonvolatile semiconductor storage devices, research and development are being conducted on ferroelectric memory (FeRAM), magnetic memory (MRAM), phase-change memory (PRAM), and nonvolatile memory elements based on various other principles. Of these, MRAM is regarded as a promising candidate to satisfy the performance requirements described above to replace DRAM. However, the number of overwrite operations (>1016) described above as a performance requirement assumes the number of accesses performed over ten years when overwriting every 30 ns. In the case of memory with nonvolatile properties, a refresh cycle is unnecessary, so that even when used in the same applications as DRAM, this many operations may not be necessary. At present, MRAM has reached a performance level at which more than 1012 overwrite operations are possible, and switching times are also short (<10 ns). Hence MRAM is regarded as much more feasible for application compared with other technologies which are candidates for nonvolatile storage devices.
The most serious problems with such MRAM devices are the large cell area, and the high bit cost which this entails. Currently marketed MRAM products with a small capacity of approximately 4 Mbits are current-induced magnetic field overwrite type devices, with cell areas of 20 to 30 F2 (where F is the minimum process dimension of the manufacturing process) or greater. That is, the cell areas of currently marketed MRAMs are too large, and their use as DRAM overwrite technology is not practical. It is under these circumstances that two potentially breakthrough technologies are changing the state of the field. One is MTJs (magnetic tunnel junctions) using an MgO tunnel insulating film, by which means magnetoresistances of 200% or higher are easily obtained (D. D. Djayaprawira et al, “230% room-temperature magnetoresistance in CoFeB/MgO/CoFeB magnetic tunnel junctions”, Applied Physics Letters, Vol. 86, 092502, 2005). The other is current-induced magnetization switching. This current-induced magnetization switching not only avoids the problem of an increase in the magnetic field (reversal magnetic field) required for overwriting (magnetization reversal) in minute cells, which was a critical defect of the current-induced magnetic field overwrite method, but in fact is an overwrite method having the advantage of reducing the write energy according to the scaling, that is, as the element is made finer the write energy is also reduced. By means of this current-induced magnetization switching method, a configuration is possible in which one MTJ is operated by one transistor, so that ideally cell areas may be 6 to 8 F2, on a par with current DRAM (J. Hayakawa et al, “Current-induced magnetization switching in MgO barrier based magnetic tunnel junctions with CoFeB/Ru/CoFeB synthetic ferrimagnetic free layer”, Japanese Journal of Applied Physics, Vol. 45, No. 40, L1057-L1060, 2006). Further, a one diode-one MTJ configuration has also been proposed, aiming at small cell areas (approximately 4 F2) on a par with flash memory and similar (Japanese Patent Application Laid-open No. 2004-179483). And, circuit simplification and reduction of the cell size of a one transistor-one MTJ circuit to be comparable to that of DRAM has also been proposed (Japanese Patent Application Laid-open No. 2006-128579). This simplification is achieved in an element provided with a driving layer the magnetization direction of which is substantially fixed in the layering direction by restricting the current polarity to only one polarity, so that the number of transistors is reduced from two types to one type.
However, in the one diode-one MTJ proposal, switching is performed by currents under a forward-direction bias and a reverse-direction bias via a diode. That is, switching is performed by means of the current of a forward-direction bias (forward-direction current) and the current of a reverse-direction bias, and so the principle of performing switching by means of the current polarity is unchanged. Here, a diode is originally provided in order to select an MTJ during write, erase, and read operations without causing disturbances, and leakage currents flow not only in the reverse direction, but in the forward direction also. Hence in the above proposal which adopts switching by leakage currents under reverse-direction bias as a principle of operation, a current of approximately the value used in switching also flows in the forward direction at low voltages, and the effect in preventing disturbances becomes insufficient. That is, if switching can be performed by a reverse-bias leakage current, then current also flows at low voltages under a forward-direction bias, and so problems of disturbances occur similarly to that of simple matrix-type memory devices with no element selection switches, and as a result, highly integrated elements cannot be realized. Thus, in order to realize a cross-point type memory device using a one diode-one MTJ configuration having a minimum cell area of 4 F2, current-induced magnetization switching methods of the past, which employ switching by current polarity as the principle of operation, cannot be adopted.
Further, the one transistor-one MTJ circuit proposed in Japanese Patent Application Laid-open No. 2006-128579, in which elements are provided in the driving layer, the magnetization direction of which is substantially fixed in the layering direction, is a method of inducing spin precession by injecting spin from the driving layer into the free layer to perform switching. However, in a method based on the principle of inducing spin precession by spin injection from the driving layer, there is the problem that the orientation (parallel or antiparallel) of the free layer (storage layer) and the pinned layer (layer with fixed direction of magnetization) tends toward one of these. Further, in this method there are also concerns that the orientation of the magnetization of the pinned layer (layer with fixed direction of magnetization) may change, and so again there is the problem of decreased reliability, here with respect to realizing a number of overwrite operations comparable to that of DRAM. Consequently, the proposal of a one transistor-one MTJ circuit, in which switching is performed by current with only one polarity, is also difficult to implement.